DRA722_17 Datasheet, PDF(205/408 Page) Texas Instruments – Infotainment Applications Processor

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DRA722_17 Datasheet, PDF (205/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726

SPRS956B â MARCH 2016 â REVISED JANUARY 2017

Table 7-9. Manual Functions Mapping for VIN1A (IOSET2/3) and VIN1B (IOSET4) and VIN2B (IOSET8) (continued)

BA BALL NAME

VIP_MANUAL7

VIP_MANUAL12

CFG REGISTER

MUXMODE

LL

A_DELAY G_DELAY A_DELAY G_DELAY

2

3(1)

3(1)

4(1)

4(1)

5

6

(ps)

(ps)

(ps)

(ps)

A1 vout1_d23

1627

1035

1726

1116

CFG_VOUT1_D23_IN

-

vin2a_d7 vin1a_d7 vin1a_d7

-

-

-

0

G1 vout1_d3

2427

429

2853

167

CFG_VOUT1_D3_IN

-

vin2a_d19 vin1a_d19 vin1a_d19

-

-

-

1

E9 vout1_d4

2351

412

2845

85

CFG_VOUT1_D4_IN

-

vin2a_d20 vin1a_d20 vin1a_d20

-

-

-

F9 vout1_d5

1634

983

1729

1076

CFG_VOUT1_D5_IN

-

vin2a_d21 vin1a_d21 vin1a_d21

-

-

-

F8 vout1_d6

1776

880

2736

107

CFG_VOUT1_D6_IN

-

vin2a_d22 vin1a_d22 vin1a_d22

-

-

-

E7 vout1_d7

2272

351

2757

53

CFG_VOUT1_D7_IN

-

vin2a_d23 vin1a_d23 vin1a_d23

-

-

-

E8 vout1_d8

1724

898

1819

990

CFG_VOUT1_D8_IN

-

vin2a_d8 vin1a_d8 vin1a_d8

-

-

-

D9 vout1_d9

2281

566

2804

195

CFG_VOUT1_D9_IN

-

vin2a_d9 vin1a_d9 vin1a_d9

-

-

-

B1 vout1_de

1734

749

1828

842

CFG_VOUT1_DE_IN

-

vin2a_de0 vin1a_de0 vin1a_de0

-

-

-

0

B1 vout1_fld

0

0

0

0

CFG_VOUT1_FLD_IN

-

vin2a_clk0 vin1a_clk0 vin1a_clk0

-

-

-

1

C1 vout1_hsync 1634

606

2399

0

CFG_VOUT1_HSYNC_I

-

vin2a_hsyn vin1a_hsyn vin1a_hsyn

-

-

-

1

N

c0

c0

c0

E1 vout1_vsync 1887

0

2068

0

CFG_VOUT1_VSYNC_I

-

vin2a_vsyn vin1a_vsyn vin1a_vsyn

-

-

-

1

N

c0

c0

c0

(1) Some signals listed are virtual functions that present alternate multiplexing options. These virtual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or

CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration

Registers.

Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring

the use of Manual IO Timings Modes. See Table 7-10 Manual Functions Mapping for VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9) for a definition

of the Manual modes.

Table 7-10 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-10. Manual Functions Mapping for VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9)

BALL

R6

T9

P9

P4

R3

BALL NAME

gpmc_a0

gpmc_a1

gpmc_a11

gpmc_a12

gpmc_a13

VIP_MANUAL8

VIP_MANUAL13

A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)

1891

427

2176

0

1713

513

2109

0

1797

317

2036

0

0

0

0

0

1876

391

2144

0

CFG REGISTER

CFG_GPMC_A0_IN

CFG_GPMC_A1_IN

CFG_GPMC_A11_IN

CFG_GPMC_A12_IN

CFG_GPMC_A13_IN

MUXMODE

3

4

5

-

vin2a_d0

-

-

vin2a_d1

-

-

vin2a_fld0

-

-

vin2a_clk0

-

-

vin2a_hsync0

-

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Timing Requirements and Switching Characteristics 205

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