DRA722_17 Datasheet, PDF (192/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 7-2. Modes Summary (continued)
Virtual or Manual IO Mode Name
Data Manual Timing Mode
GMAC_RMII1_MANUAL1
GMAC RMII1 Timings
VIP
VIP_MANUAL1
VIN2A (IOSET10) Rise-Edge Capture Mode Timings
VIP_MANUAL2
VIN2A (IOSET10) Fall-Edge Capture Mode Timings
VIP_MANUAL3
VIN2A (IOSET4/5/6) Rise-Edge Capture Mode Timings
VIP_MANUAL4
VIN2B (IOSET1/2/7) Rise-Edge Capture Mode Timings
VIP_MANUAL5
VIN2A (IOSET4/5/6) Fall-Edge Capture Mode Timings
VIP_MANUAL6
VIN2B (IOSET1/2/7) Fall-Edge Capture Mode Timings
VIP_MANUAL7
VIN1A (IOSET2/3) and VIN1B (IOSET4) and VIN2B (IOSET8) Rise-Edge Capture
Mode Timings
VIP_MANUAL8
VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9) Rise-Edge Capture Mode Timings
VIP_MANUAL9
VIN1B (IOSET6) Rise-Edge Capture Mode Timings
VIP_MANUAL10
VIN1B (IOSET5) and VIN2B (IOSET9) Rise-Edge Capture Mode Timings
VIP_MANUAL11
VIN1B (IOSET5) and VIN2B (IOSET9) Fall-Edge Capture Mode Timings
VIP_MANUAL12
VIN1A (IOSET2/3) and VIN1B (IOSET4) and VIN2B (IOSET8) Fall-Edge Capture Mode
Timings
VIP_MANUAL13
VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9) Fall-Edge Capture Mode Timings
VIP_MANUAL14
VIN1B (IOSET6) Fall-Edge Capture Mode Timings
VIP_MANUAL15
VIN1A (IOSET8/9/10) Rise-Edge Capture Mode Timings
VIP_MANUAL16
VIN1A (IOSET8/9/10) Fall-Edge Capture Mode Timings
HDMI, EMIF, Timers, I2C, HDQ/1-Wire, UART, McSPI, USB, SATA, PCIe, DCAN, GPIO, KBD, PWM, ATL, JTAG, TPIU, RTC, SDMA,
INTC, MLB
No Virtual or Manual IO Timing Mode Required All Modes
7.6 Video Input Ports (VIP)
The Device includes 1 Video Input Ports (VIP).
Table 7-3, Figure 7-4 and Figure 7-5 present timings and switching characteristics of the VIPs.
CAUTION
The I/O timings provided in this section are valid only for VIN1 and VIN2 if
signals within a single IOSET are used. The IOSETs are defined in Table 7-4.
Table 7-3. Timing Requirements for VIP ^(3)(4)(5)
NO.
V1
V2
V3
V4
PARAMETER
t_c(CLK)
t_w(CLKH)
t_w(CLKL)
t_{su(CTL/DATA-CLK)}
DESCRIPTION
Cycle time, vinx_clki ^{(3) (5)}
Pulse duration, vinx_clki high ^{(3) (5)}
Pulse duration, vinx_clki low ^{(3) (5)}
Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition ^{(3) (4) (5)}
V6
t_{h(CLK-CTL/DATA)}
Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci)
and Data (vinx_dn) valid from vinx_clki transition ^{(3) (4) (5)}
(1) For maximum frequency of 165 MHz.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a, 2b.
(4) n in dn = 0 to 7 when x = 1b, 2b.
n = 0 to 23 when x = 1a, 2a.
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
MIN
6.06 ⁽²⁾
0.45*P ⁽²⁾
0.45*P ⁽²⁾
3.11 ⁽²⁾
-0.05 ⁽²⁾
MAX
UNIT
ns
ns
ns
ns
ns
192 Timing Requirements and Switching Characteristics
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