DRA722_17 Datasheet, PDF (387/408 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
DDR Address and Control Input Buffers
Processor
Address and Control
Output Buffer
Address and Control
Terminator
Rtt
A1
A2
A3
A4
A3
AT
Vtt
Figure 8-46. ADDR_CTRL Topology for Four x8 DDR3 Devices
SPRS906_PCB_DDR3_07
8.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
Figure 8-47 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-48
shows the corresponding ADDR_CTRL routing.
DDR_1V5
Rcp
Cac
A2
A3
A4
A3
AT
A2
A3
A4
A3
AT
Rcp
0.1 µF
=
SPRS906_PCB_DDR3_08
Figure 8-47. CK Routing for Four Single-Side DDR3 Devices
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 387
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726