DRA722_17 Datasheet, PDF (345/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
• LL values shown are the recommended max PCB trace inductance between a decoupling capacitor’s
power supply and ground reference terminals when viewed from the decoupling capacitor with a
“theoretical shorted” applied across the Processor’s supply inputs to ground reference.
• Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb
frequency range that limits transient noise drops to no more than 5% of min supply voltage during max
transient current events.
• Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a
reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance
below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar
spreading and internal package inductances.
Table 8-3. Recommended PDN and Decoupling Characteristics ^{(1)(2)(3)(4)(5)}
PDN Analysis:
Static
Dynamic
Number of Recommended Decoupling Capacitors
per Supply
Supply
Max R_eff
(7)
[mΩ]
Dec. Cap.
Max LL^{(8) (6)}
[nH]
Max
Impedance
[mΩ]
Frequency
range
of Interest
100 220
nF⁽⁶⁾ nF
470
nF
1μF
2.2
μF
4.7
μF
[MHz]
10
μF
22
μF
vdd_mpu
10
2
57
≤20
8
1
1
1
1
1
1
vdd_dsp, vdd_gpu,
vdd_iva
13
2.5
54
≤20
8
1
1
1
1
1
1
1
vdd
27
2
87
≤50
6
1
1
1
1
1
vdds_ddr1
10
2.5
200
≤100
8
4
2
2
1
cap_vbbldo_dsp
N/A
6
N/A
N/A
1
cap_vbbldo_gpu
N/A
6
N/A
N/A
1
cap_vbbldo_iva
N/A
6
N/A
N/A
1
cap_vbbldo_mpu
N/A
6
N/A
N/A
1
cap_vddram_core1
N/A
6
N/A
N/A
1
cap_vddram_core3
N/A
6
N/A
N/A
1
cap_vddram_core4
N/A
6
N/A
N/A
1
cap_vddram_dsp
N/A
6
N/A
N/A
1
cap_vddram_gpu
N/A
6
N/A
N/A
1
cap_vddram_iva
N/A
6
N/A
N/A
1
cap_vddram_mpu
N/A
6
N/A
N/A
1
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Specifications chapter.
(2) ESL must be as low as possible and must not exceed 0.5 nH.
(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)
based on the Recommended Operating Conditions table of the Specifications chapter.
(4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor
power balls.
(5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.
(6) High-frequency (30 to 70MHz) PCB decoupling capacitors
(7) Maximum R_eff from SMPS to Processor.
(8) Maximum Loop Inductance for decoupling capacitor.
8.3.5 Power Supply Mapping
TPS65917 or TPS659039 are the Power Management ICs (PMICs) that should be used for the Device
designs. TI requires use of these PMICs for the following reasons:
• TI has validated their use with the Device
• Board level margins including transient response and output accuracy are analyzed and optimized for
the entire system
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Applications, Implementation, and Layout 345
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