DRA722_17 Datasheet, PDF (319/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-127. Switching Characteristics for MMC4 - High Speed Mode ⁽²⁾ (continued)
NO.
HS2L
PARAMETER
t_w(clkL)
DESCRIPTION
Pulse duration, mmc4_clk low
HS5
t_d(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
HS6 t_d(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
MIN
0.5*P-
0.270 ⁽¹⁾
-8.8
-8.8
MAX
6.6
6.6
UNIT
ns
ns
ns
HS1
HS2L
HS2H
mmcj_clk
HS3
HS4
mmcj_cmd
HS7
HS8
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_09
Figure 7-86. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Receiver Mode
HS1
HS2H
HS2L
mmcj_clk
HS5
HS5
mmcj_cmd
HS6
HS6
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_10
Figure 7-87. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Transmitter Mode
7.25.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
Figure 7-88, Figure 7-89, and Table 7-128, through Table 7-131 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode.
Table 7-128. Timing Requirements for MMC3 - SDR12 Mode ⁽¹⁾
NO. PARAMETER
SDR125 t_{su(cmdV-clkH)}
SDR126 t_h(clkH-cmdV)
SDR127 t_su(dV-clkH)
SDR128 t_h(clkH-dV)
(1) i in [i:0] = 7
DESCRIPTION
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
MIN
25.99
1.6
25.99
1.6
MAX
UNIT
ns
ns
ns
ns
Table 7-129. Switching Characteristics for MMC3 - SDR12 Mode ⁽²⁾
NO. PARAMETER
SDR120 fop(clk)
SDR121 t_w(clkH)
DESCRIPTION
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
MIN
0.5*P-
0.270 ⁽¹⁾
MAX
24
UNIT
MHz
ns
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Timing Requirements and Switching Characteristics 319
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