DRA722_17 Datasheet, PDF (213/408 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
D2
D1
D3
D4
vouti_clk
D6
vouti_clk
Falling-edge Clock Reference
Rising-edge Clock Reference
vouti_vsync
D6
vouti_hsync
vouti_d[23:0]
vouti_de
D5
data_1 data_2
D6
data_n
D6
vouti_fld
odd
even
SWPS049-018
Figure 7-6. DPI Video Output^(1)(2)(3)
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.
In Table 7-16 are presented the specific groupings of signals (IOSET) for use with VOUT2.
SIGNALS
vout2_d23
vout2_d22
vout2_d21
vout2_d20
vout2_d19
vout2_d18
vout2_d17
vout2_d16
vout2_d15
vout2_d14
vout2_d13
vout2_d12
vout2_d11
vout2_d10
BALL
F2
F3
D1
E2
D2
F4
C1
E4
F5
E6
D3
F6
D5
C2
Table 7-16. VOUT2 IOSETs
IOSET1
MUX
4
4
4
4
4
4
4
4
4
4
4
4
4
4
BALL
AA4
AB3
AB9
AA3
D17
G16
A21
C18
A17
B17
B16
D15
A15
B15
IOSET2
MUX
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 213
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726