DRA722_17 Datasheet, PDF (138/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Instance Name
L3_MAIN
L4_CFG
L4_PER1
L4_PER2
L4_PER3
L4_WKUP
MAILBOX1
MAILBOX2
MAILBOX3
MAILBOX4
MAILBOX5
MAILBOX6
MAILBOX7
MAILBOX8
MAILBOX9
MAILBOX10
MAILBOX11
MAILBOX12
MAILBOX13
Table 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
L3_CLK1
L3_CLK2
L4_CFG_CLK
L4_PER1_CLK
L4_PER2_CLK
L4_PER3_CLK
L4_WKUP_CLK
MAILBOX1_FLCK
MAILBOX2_FLCK
MAILBOX3_FLCK
MAILBOX4_FLCK
MAILBOX5_FLCK
MAILBOX6_FLCK
MAILBOX7_FLCK
MAILBOX8_FLCK
MAILBOX9_FLCK
MAILBOX10_FLCK
MAILBOX11_FLCK
MAILBOX12_FLCK
MAILBOX13_FLCK
Clock
Type
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Max. Clock
Allowed (MHz)
L3_CLK
L3_CLK
133
133
133
133
38.4
266
266
266
266
266
266
266
266
266
266
266
266
266
PRCM Clock Name
L3MAIN1_L3_GICLK
L3INSTR_L3_GICLK
L4CFG_L3_GICLK
L4PER_L3_GICLK
L4PER2_L3_GICLK
L4PER3_L3_GICLK
WKUPAON_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
PLL / OSC /
Source Name
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC1
DPLL_ABE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
138 Specifications
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