DRA722_17 Datasheet, PDF (263/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for QSPI. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-45 Manual
Functions Mapping for QSPI for a definition of the Manual modes.
Table 7-45 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
BALL
BALL NAME
T7
gpmc_a3
P6
gpmc_a4
R3
gpmc_a13
T2
gpmc_a14
U2
gpmc_a15
U1
gpmc_a16
U1
gpmc_a16
P3
gpmc_a17
R2
gpmc_a18
P2
gpmc_cs2
P1
gpmc_cs3
Table 7-45. Manual Functions Mapping for QSPI
QSPI1_MANUAL1
A_DELAY (ps)
G_DELAY (ps)
0
0
0
0
0
0
2247
1186
2176
1197
2229
1268
0
0
2251
1217
0
0
0
0
0
0
CFG REGISTER
CFG_GPMC_A3_OUT
CFG_GPMC_A4_OUT
CFG_GPMC_A13_IN
CFG_GPMC_A14_IN
CFG_GPMC_A15_IN
CFG_GPMC_A16_IN
CFG_GPMC_A16_OUT
CFG_GPMC_A17_IN
CFG_GPMC_A18_OUT
CFG_GPMC_CS2_OUT
CFG_GPMC_CS3_OUT
MUXMODE
1
qspi1_cs2
qspi1_cs3
qspi1_rtclk
qspi1_d3
qspi1_d2
qspi1_d0
qspi1_d0
qspi1_d1
qspi1_sclk
qspi1_cs0
qspi1_cs1
7.18 Multichannel Audio Serial Port (McASP)
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission
(DIT).
The device have integrated 8 McASP modules (McASP1-McASP8) with:
• McASP1 and McASP2 modules supporting 16 channels with independent TX/RX clock/sync domain
• McASP3 through McASP8 modules supporting 4 channels with independent TX/RX clock/sync domain
NOTE
For more information, see the Serial Communication Interface section of the Device TRM.
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-46, Table 7-47, Table 7-48 and Figure 7-41 present Timing Requirements for McASP1 to
McASP8.
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 263
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