DRA722_17 Datasheet, PDF (106/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 4-16. McASP Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
BALL
mcasp8_fsr
McASP8 Receive Frame Sync
IO
A17
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between V_IH and V_IL must be less than V_HYS.
4.4.14 Universal Serial Bus (USB)
NOTE
For more information, see: Serial Communication Interface / SuperSpeed USB DRD
Subsystem section of the device TRM.
Table 4-17. Universal Serial Bus Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
Universal Serial Bus 1
usb1_dp
USB1 USB2.0 differential signal pair (positive)
IODS
AD12
usb1_dm
USB1 USB2.0 differential signal pair (negative)
IODS
AC12
usb1_drvvbus
usb_rxn0⁽¹⁾
usb_rxp0⁽¹⁾
usb_txn0⁽¹⁾
usb_txp0⁽¹⁾
USB1 Drive VBUS signal
USB1 USB3.0 receiver negative lane
USB1 USB3.0 receiver positive lane
USB1 USB3.0 transmitter negative lane
USB1 USB3.0 transmitter positive lane
O
IDS
IDS
ODS
ODS
AB10
AF12
AE12
AC11
AD11
Universal Serial Bus 2
usb2_dp
USB2 USB2.0 differential signal pair (positive)
IO
AE11
usb2_dm
USB2 USB2.0 differential signal pair (negative)
IO
AF11
usb2_drvvbus
USB2 Drive VBUS signal
O
AC10
Universal Serial Bus 3
usb3_ulpi_d0
USB3 - ULPI 8-bit data bus
IODS
AC3 / V6
usb3_ulpi_d1
USB3 - ULPI 8-bit data bus
IODS
AC9 / U6
usb3_ulpi_d2
USB3 - ULPI 8-bit data bus
IO
AC6 / U5
usb3_ulpi_d3
USB3 - ULPI 8-bit data bus
IO
AC7 / V5
usb3_ulpi_d4
USB3 - ULPI 8-bit data bus
IO
AC4 / V4
usb3_ulpi_d5
USB3 - ULPI 8-bit data bus
IO
AD4 / V3
usb3_ulpi_d6
USB3 - ULPI 8-bit data bus
IO
AB4 / Y2
usb3_ulpi_d7
USB3 - ULPI 8-bit data bus
IO
AC5 / W2
usb3_ulpi_nxt
USB3 - ULPI next
I
AC8 / U7
usb3_ulpi_dir
USB3 - ULPI bus direction
I
AD6 / V7
usb3_ulpi_stp
USB3 - ULPI stop
O
AB8 / V9
usb3_ulpi_clk
USB3 - ULPI functional clock
I
AB5 / W9
(1) Signals are enabled by selecting the correct field in the PCIE_B1C0_MODE_SEL register. There are no CTRL_CORE_PAD* register
involved.
4.4.15 SATA
NOTE
For more information, see the Serial Communication Interfaces / SATA section of the device
TRM.
106 Terminal Configuration and Functions
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