HD64F3437TF16 Datasheet, PDF (99/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

4.3.2 Interrupt-Related Registers
The interrupt-related registers are the system control register (SYSCR), IRQ sense control register
(ISCR), IRQ enable register (IER), and keyboard matrix interrupt mask registers (KMIMR and
KMIMRA).
Table 4.3 Registers Read by Interrupt Controller
Name
System control register
IRQ sense control register
IRQ enable register
Keyboard matrix interrupt mask register
Keyboard matrix interrupt mask register A
Abbreviation
SYSCR
ISCR
IER
KMIMR
KMIMRA
Read/Write
R/W
R/W
R/W
R/W
R/W
Address
H'FFC4
H'FFC6
H'FFC7
H'FFF1
H'FFF3
System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
2
1
XRST NMIEG HIE
1
0
0
R
R/W
R/W
0
RAME
1
R/W
The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register.
Bit 2—NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the
falling or rising edge of the NMI input signal.
Bit 2: NMIEG
0
1
Description
An interrupt is generated on the falling edge of NMI.
An interrupt is generated on the rising edge of NMI.
(Initial state)
See section 3.2, System Control Register, for information on the other SYSCR bits.
IRQ Sense Control Register (ISCR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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