HD64F3437TF16 Datasheet, PDF(545/752 Page) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

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HD64F3437TF16 Datasheet, PDF (545/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

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Automatic Alignment of SCI Bit Rate

Start

bit

D0

D1

D2

D3

D4

D5

D6

D7

Stop

bit

This low period (9 bits) is measured (H'00 data)

High for at

least 1 bit

Figure 21.8 Measurement of Low Period in Data Transmitted from Host

When started in boot mode, the H8/3437SF measures the low period in asynchronous SCI data

(H'00) transmitted from the host. The data format is eight data bits, one stop bit, and no parity bit.

From the measured low period (9 bits), the H8/3437SF computes the hostâs bit rate. After aligning

its own bit rate, the H8/3437SF sends the host one byte of H'00 data to indicate that bit-rate

alignment is completed. The host should check that this alignment-completed indication is

received normally and send one H'55 byte back to the H8/3437SF. If the alignment-completed

indication is not received normally, the H8/3437F should be reset, then restarted in boot mode to

measure the low period again. There may be some alignment error between the hostâs and

H8/3437SFâs bit rates, depending on the hostâs transmission bit rate and the H8/3437SFâs system

clock frequency (fOSC). To have the SCI operate normally, set the hostâs transfer bit rate to 2400,

4800, or 9600 bps.

Table 21.7 lists typical host transfer bit rates and indicates the system clock frequency ranges over

which the H8/3437SF can align its bit rate automatically. Boot mode should be used within these

frequency ranges.

Table 21.7 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by

H8/3437SF

Host Bit Rate

9600 bps

4800 bps

2400 bps

System Clock Frequencies (fOSC) Permitting Automatic Bit-Rate

Alignment by H8/3437SF

8 MHz to 16 MHz

4 MHz to 16 MHz

2 MHz to 16 MHz

RAM Area Allocation in Boot Mode: In boot mode, the 128 bytes from H'FF00 to H'FF7F are

reserved for use by the boot program, as shown in figure 21.9. The user program is transferred into

the area from H'F780 to H'FDFF (1664 bytes). The boot program area can be used after the

transition to execution of the user program transferred into RAM. If a stack area is needed, set it

within the user program.

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