HD64F3437TF16 Datasheet, PDF (348/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

14.1.2 Input and Output Pins
Table 14.1 lists the input and output pins of the host interface module.
Table 14.1 H/F Input/Output Pins
Name
Abbreviation Port
I/O
Function
I/O read
I/O write*
Chip select 1
IOR
IOW
EIOW
CS₁
P8₃
Input
Host interface read signal
P8₄
Input
Host interface write signal
P9₁
P8₂
Input
Host interface chip select signal for
IDR1, ODR1, STR1
Chip select 2*
Command/data
CS₂
ECS₂
HA₀
P8₅
Input
Host interface chip select signal for
P9₀
IDR2, ODR2, STR2
P8₀
Input
Host interface address select signal
In host read access, this signal
selects the status registers (STR1,
STR2) or data registers (ODR1,
ODR2). In host write access to the
data registers (IDR1, IDR2), this
signal indicates whether the host is
writing a command or data.
Data bus
HDB₇–HDB₀
P3₇–P3₀ I/O
Host interface data bus (single-chip
mode)
XDB₇–XDB₀
PB₇–PB₀ I/O
Host interface data bus (expanded
modes)
Host interrupt 1 HIRQ₁
P4₄
Output Interrupt output 1 to host
Host interrupt 11 HIRQ₁₁
P4₃
Output Interrupt output 11 to host
Host interrupt 12 HIRQ₁₂
P4₅
Output Interrupt output 12 to host
Gate A₂₀
GA₂₀
P8₁
Output A₂₀ gate control signal output
Note: * Selection between IOW and EIOW, and between CS₂ and ECS₂, is by the STAC bit in
STCR. IOW and CS₂ are used when STAC is 0. EIOW and ECS₂ are used when STAC is 1.
In this manual, both are referred to as IOW and CS₂.
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