HD64F3437TF16 Datasheet, PDF (27/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

23.4.1 DC Characteristics ................................................................................................ 580
23.4.2 AC Characteristics ................................................................................................ 585
23.4.3 A/D Converter Characteristics.............................................................................. 591
23.4.4 D/A Converter Characteristics.............................................................................. 592
23.4.5 Flash Memory Characteristics .............................................................................. 593
23.5 MCU Operational Timing.................................................................................................. 595
23.5.1 Bus Timing ........................................................................................................... 595
23.5.2 Control Signal Timing .......................................................................................... 596
23.5.3 16-Bit Free-Running Timer Timing...................................................................... 598
23.5.4 8-Bit Timer Timing............................................................................................... 599
23.5.5 Pulse Width Modulation Timer Timing................................................................ 600
23.5.6 Serial Communication Interface Timing .............................................................. 601
23.5.7 I/O Port Timing..................................................................................................... 602
23.5.8 Host Interface Timing ........................................................................................... 602
23.5.9 I²C Bus Timing (Option) ...................................................................................... 603
23.5.10 Reset Output Timing............................................................................................. 604
23.5.11 External Clock Output Timing.............................................................................. 604
Appendix A CPU Instruction Set.................................................................................... 605
A.1 Instruction Set List ............................................................................................................. 605
A.2 Operation Code Map.......................................................................................................... 613
A.3 Number of States Required for Execution ......................................................................... 615
Appendix B Internal I/O Register................................................................................... 621
B.1 Addresses ........................................................................................................................... 621
B.2 Function ............................................................................................................................. 626
Appendix C I/O Port Block Diagrams .......................................................................... 684
C.1 Port 1 Block Diagram ........................................................................................................ 684
C.2 Port 2 Block Diagram ........................................................................................................ 685
C.3 Port 3 Block Diagram ........................................................................................................ 686
C.4 Port 4 Block Diagrams ....................................................................................................... 687
C.5 Port 5 Block Diagrams ....................................................................................................... 691
C.6 Port 6 Block Diagrams ....................................................................................................... 694
C.7 Port 7 Block Diagrams ....................................................................................................... 698
C.8 Port 8 Block Diagrams ....................................................................................................... 699
C.9 Port 9 Block Diagrams ....................................................................................................... 705
C.10 Port A Block Diagram........................................................................................................ 711
C.11 Port B Block Diagram........................................................................................................ 712
Appendix D Port States in Each Processing State ..................................................... 713
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