HD64F3437TF16 Datasheet, PDF (343/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

• Countermeasure
Figure 13.19 shows the recommended program flow.
Write data to ICDR
Yes
Transmit
data present?
No
Read IRIC in ICSR
No
IRIC = 1?
Yes
Read ACKB in ICSR
No
ACKB = 1?
Yes
Read SCL
No
SCL = 0?
Yes
Write 0 to BBSY and
0 to SCP in ICSR
Figure 13.19 Recommended Program Flow
• Additional Note
When switching from master receive mode to master transmit mode, ensure that TRS is set to 1
before the last receive data is latched by reading ICDR.
• Precautions when Clearing the IRIC Flag when Using the Wait Function
If the SCL rise time exceeds the specified duration when using the wait function in the I²C bus
interface’s master mode, or if there is a slave device that keeps SCL low and applies a wait
state, read SCL and clear the IRIC flag only after determining that SCL has gone low, as
shown below.
If the IRIC flag is cleared to 0 when WAIT is set to 1 and while the SCL high level duration is
being extended, the SDA value may change before SCL falls, erroneously resulting in a start or
stop condition.
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