HD64F3437TF16 Datasheet, PDF (235/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

9.6.2 Contention between TCNT Write and Increment
If a timer counter increment pulse is generated during the T₃ state of a write cycle to the timer
counter, the write takes priority and the timer counter is not incremented.
Figure 9.11 shows this type of contention.
Write cycle: CPU writes to TCNT
T₁
T₂
T₃
ø
Internal address bus
TCNT address
Internal write signal
TCNT clock pulse
TNCT
N
M
Write data
Figure 9.11 TCNT Write-Increment Contention
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