HD64F3437TF16 Datasheet, PDF (576/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

22.3 Software Standby Mode
22.3.1 Transition to Software Standby Mode
To enter software standby mode, set the standby bit (SSBY) in the system control register
(SYSCR) to 1, then execute the SLEEP instruction.
In software standby mode, the system clock stops and chip functions halt, including both CPU
functions and the functions of the on-chip supporting modules. Power consumption is reduced to
an extremely low level. The on-chip supporting modules and their registers are reset to their initial
states, but as long as a minimum necessary voltage supply is maintained, the contents of the CPU
registers and on-chip RAM remain unchanged.
22.3.2 Exit from Software Standby Mode
The chip can be brought out of software standby mode by an RES input, STBY input, or external
interrupt input at the NMI pin, IRQ₀ to IRQ₂ pins, or IRQ₆ pin (including KEYIN₀ to KEYIN₁₅).
Exit by Interrupt: When an NMI, IRQ₀, IRQ₁, IRQ₂, or IRQ₆ interrupt request signal is input, the
clock oscillator begins operating. After the waiting time set in bits STS2 to STS0 of SYSCR, a
stable clock is supplied to the entire chip, software standby mode is released, and interrupt
exception-handling begins. IRQ₃, IRQ₄, IRQ₅, and IRQ₇ interrupts should be disabled before the
transition to software standby (clear IRQ3E, IRQ4E, IRQ5E, and IRQ7E to 0).
Exit by RES Pin: When the RES input goes low, the clock oscillator begins operating. When
RES is brought to the high level (after allowing time for the clock oscillator to settle), the CPU
starts reset exception handling. Be sure to hold RES low long enough for clock oscillation to
stabilize.
Exit by STBY Pin: When the STBY input goes low, the chip exits from software standby mode
to hardware standby mode.
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