HD64F3437TF16 Datasheet, PDF (631/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

23.5.7 I/O Port Timing
Port read/write cycle
T₁
T₂
T₃
ø
Port 1 to
port 9 (input)
Port A, B
Port 1* to
port 9 (output)
Port A, B
Note: * Except P9₆ and P7₇ to P7₀
t_PRS
t_PRH
t_PWD
Figure 23.21 I/O Port Input/Output Timing
23.5.8 Host Interface Timing
(1) Host Interface Read Timing
CS/HA₀
HA₀
IOR
t_HAR
t_HRPW
t_HRD
t_HRA
t_HRF
HDB₇ to HDB₀
HIRQ_i*
(i = 1, 11, 12)
Valid data
t_HIRQ
Note: * Rising edge timing is the same as in port 4 output timing. Refer to figure 23.21.
Figure 23.22 Host Interface Read Timing
602