HD64F3437TF16 Datasheet, PDF (619/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Table 23.23 I²C Bus Timing
Conditions: V_CC = 3.0 V to 5.5 V, V_CCB = 3.0 V to 5.5 V, V_SS = 0 V, Ta = –20°C to +75°C
(regular specifications), Ta = –40 to +85˚C (wide-range specifications),
ø = 5 MHz to maximum operating frequency
Item
Symbol Min
Typ
SCL clock
t _SCL
12 t_cyc
—
cycle time
SCL clock
t _SCLH
3 t_cyc
—
high pulse
width
SCL clock
t _SCLL
5 t_cyc
—
low pulse
width
SCL and SDA t_Sr
—
—
rise time
20 + 0.1C_b —
SCL and SDA t_Sf
fall time
—
—
20 + 0.1C_b —
SDA bus-free t_BUF
5 t_cyc
—
time
SCL start
t _STAH
3 t_cyc
—
condition
hold time
SCL resend t_STAS
3 t_cyc
—
start condition
setup time
SDA stop
t _STOS
3 t_cyc
—
condition
setup time
SDA data
t _SDAS
0.5 t_cyc
—
setup time
SDA data
t _SDAH
0
—
hold time
SDA load
C_b
—
—
capacitance
Max
—
—
—
1000
300
300
300
—
—
—
—
—
—
400
Unit Test Conditions Note
ns
Fig. 23.24
ns
ns
ns Normal mode
100 kbits/s (max)
High-speed mode
400 kbits/s (max)
ns Normal mode
100 kbits/s (max)
High-speed mode
400 kbits/s (max)
ns
ns
ns
ns
ns
ns
pF
590