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HD64F3437TF16 Datasheet, PDF (65/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device. | |||
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2.5.2 Arithmetic Operations
Table 2.5 describes the arithmetic instructions. See figure 2.6 in section 2.5.4, Shift Operations,
for their object codes.
Table 2.5 Arithmetic Instructions
Instruction
ADD
SUB
Size*
B/W
ADDX
B
SUBX
INC
B
DEC
ADDS
W
SUBS
DAA
B
DAS
MULXU
B
DIVXU
B
CMP
B/W
NEG
B
Note: * Size: Operand size
B: Byte
W: Word
36
Function
Rd ± Rs â Rd, Rd + #imm â Rd
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register.
Immediate data cannot be subtracted from data in a general register.
Word data can be added or subtracted only when both words are in
general registers.
Rd ± Rs ± C â Rd, Rd ± #imm ± C â Rd
Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data
and data in a general register.
Rd ± #1 â Rd
Increments or decrements a general register.
Rd ± #imm â Rd
Adds or subtracts immediate data to or from data in a general
register. The immediate data must be 1 or 2.
Rd decimal adjust â Rd
Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR.
Rd à Rs â Rd
Performs 8-bit à 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.
Rd ÷ Rs â Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
Rd â Rs, Rd â #imm
Compares data in a general register with data in another general
register or with immediate data. Word data can be compared only
between two general registers.
0 â Rd â Rd
Obtains the twoâs complement (arithmetic complement) of data in a
general register.
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