HD64F3437TF16 Datasheet, PDF (695/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

ICSR—I²C Bus Status Register
Bit
Initial value
Read/Write
7
BBSY
0
R/W
6
IRIC
0
R/(W)*
5
SCP
1
W
H'D9
I²C
4
3
2
1
0
—
AL
AAS ADZ ACKB
1
0
0
0
0
— R/(W)* R/(W)* R/(W)* R/W
Acknowledge Bit
0 Receive mode: 0 is output at acknowledge output timing
Transmit mode: indicates that the receiving device has acknowledged the data
1 Receive mode: 1 is output at acknowledge output timing
Transmit mode: indicates that the receiving device has not acknowledged the data
General Call Address Recognition Flag
0 General call address not recognized
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading ADZ = 1, then writing 0
1 General call address recognized
Set when the general call address is detected in slave receive mode
Slave Address Recognition Flag
0 ^{Slave address or general call address not recognized (Initial value)}
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading AAS = 1, then writing 0
1 ^{Slave address or general call address recognized}
Set when the slave address or general call address is detected in slave receive mode
Arbitration Lost Flag
0 Bus arbitration won
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading AL = 1, then writing 0
1 Arbitration lost
Set if the internal SDA and bus line disagree at the rise of SCL in master transmit mode
Set if the internal SCL is high at the fall of SCL in master transmit mode
Start Condition/Stop Condition Prohibit
0 Writing 0 issues a start or stop condition, in combination with BBSY
1 Reading always results in 1
Writing is ignored
I²C Bus Interface Interrupt Request Flag
0 Waiting for transfer, or transfer in progress
Cleared by reading IRIC = 1, then writing 0
Bus Busy
0 Bus is free
Cleared by detection
of a stop condition
1 Bus is busy
Set by detection
of a start condition
1 Interrupt requested
Set to 1 at the following times:
Master mode
• End of data transfer
• Bus arbitration lost
Slave mode (when FS = 0)
• When the slave address is matched, and whenever a data transfer ends at timing of
a retransmit start condition after address matching or a stop condition is detected
• When a general call address is detected, and whenever a data transfer ends at timing
of a retransmit start condition after address detection or a stop condition is detected
Slave mode (when FS = 1)
• End of data transfer
Note: * Only 0 can be written, to clear the flag.
666