HD64F3437TF16 Datasheet, PDF (308/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

12.4 Interrupts
The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 12.11 indicates the
source and priority of these interrupts. The interrupt sources can be enabled or disabled by the
TIE, RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for
each interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three
sources: overrun error, framing error, and parity error.
The TXI interrupt indicates that the next transmit data can be written. The TEI interrupt indicates
that the SCI has stopped transmitting data.
Table 12.11 SCI Interrupt Sources
Interrupt
ERI
RXI
TXI
TEI
Description
Receive-error interrupt (ORER, FER, or PER)
Receive-end interrupt (RDRF)
TDR-empty interrupt (TDRE)
TSR-empty interrupt (TEND)
Priority
High
Low
12.5 Application Notes
Application programmers should note the following features of the SCI.
TDR Write: The TDRE bit in SSR is simply a flag that indicates that the TDR contents have been
transferred to TSR. The TDR contents can be rewritten regardless of the TDRE value. If a new
byte is written in TDR while the TDRE bit is 0, before the old TDR contents have been moved
into TSR, the old byte will be lost. Software should check that the TDRE bit is set to 1 before
writing to TDR.
Multiple Receive Errors: Table 12.12 lists the values of flag bits in the SSR when multiple
receive errors occur, and indicates whether the RSR contents are transferred to RDR.
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