HD64F3437TF16 Datasheet, PDF(104/752 Page) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

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HD64F3437TF16 Datasheet, PDF (104/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

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4.3.5 Interrupt Handling

Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt

requests, commands the CPU to start the hardware interrupt exception-handling sequence, and

furnishes the necessary vector number. Figure 4.4 shows a block diagram of the interrupt

controller.

NMI interrupt

IRQ0 flag

IRQ0E

*

IRQ0

interrupt

Interrupt

controller

Interrupt request

Priority

decision

Vector number

CPU

IRIC

IEIC

IICI

interrupt

I (CCR)

Note: * For edge-sensed interrupts, these AND gates change to the circuit shown below.

IRQ0 edge

IRQ0E

IRQ0 flag

SQ

IRQ0 interrupt

Figure 4.4 Block Diagram of Interrupt Controller

The IRQ interrupts and interrupts from the on-chip supporting modules (except for reset selected

for a watchdog timer overflow) all have corresponding enable bits. When the enable bit is cleared

to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These

interrupts can also all be masked by setting the CPUâs interrupt mask bit (I) to 1. Accordingly,

these interrupts are accepted only when their enable bit is set to 1 and the I bit is cleared to 0.

The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware

standby mode.

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