HD64F3437TF16 Datasheet, PDF (368/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

15.2 Register Descriptions
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRn
AD9 AD8 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — —
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R R R R R R R R R
Bits 15 to 6—A/D Conversion Data (AD9 to AD0): 10-bit data giving an A/D conversion result.
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 0.
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that always read 0. Table 15.3 indicates the pairings of analog input
channels and A/D data registers.
The CPU can always read the A/D data registers. The upper byte can be read directly, but the
lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 15.3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0
Group 1
AN₀
AN₁
AN₂
AN₃
AN₄
AN₅
AN₆
AN₇
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
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