HD64F3437TF16 Datasheet, PDF (335/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

13.3.7 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 13.11 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or
SDA input
signal
C
D
Q
Latch
C
D
Q
Latch
Match
detector
Internal
SCL or
SDA
signal
t
Sampling
clock
t: System clock
Figure 13.11 Block Diagram of Noise Canceler
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