HD64F3437TF16 Datasheet, PDF (127/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

External Clock Input: The external clock signal should have the same frequency as the desired
system clock (ø). Clock timing parameters are given in table 6.7 and figure 6.12.
Table 6.7 Clock Timing
Item
Low pulse width of external
clock input
High pulse width of external
clock input
External clock rise time
External clock fall time
Clock pulse
width low
Clock pulse
width high
Symbol
t _EXL
t _EXH
t _EXr
t _EXf
t _CL
t _CH
V_CC = 3.0 to 5.5 V
Min
Max
40
—
40
—
—
10
—
10
0.3
0.7
0.4
0.6
0.3
0.7
0.4
0.6
Unit
ns
ns
ns
ns
t _cyc
t _cyc
t _cyc
t _cyc
Test Conditions
Figure 6.12
ø ≥ 5 MHz
ø < 5 MHz
ø ≥ 5 MHz
ø < 5 MHz
Figure 23.7
EXTAL
t_EXH
t_EXL
V_CC × 0.5
t_EXr
t_EXt
Figure 6.12 External Clock Input Timing
Table 6.8 lists the external clock output stabilization delay time. Figure 6.13 shows the timing for
the external clock output stabilization delay time. The oscillator and duty correction circuit have
the function of regulating the waveform of the external clock input to the EXTAL pin. When the
specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after
the elapse of the external clock output stabilization delay time (t_DEXT). As clock signal output is not
confirmed during the t_DEXT period, the reset signal should be driven low and the reset state
maintained during this time.
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