HD64F3437TF16 Datasheet, PDF (274/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bit 2—Transmit End (TEND): This bit indicates that the serial communication interface has
stopped transmitting because there was no valid data in TDR when the last bit of the current
character was transmitted. The TEND bit is also set to 1 when the TE bit in the serial control
register (SCR) is cleared to 0.
The TEND bit is a read-only bit and cannot be modified directly. To use the TEI interrupt, first
start transmitting data, which clears TEND to 0, then set TEIE to 1.
Bit 2: TEND
0
1
Description
To clear TEND, the CPU must read TDRE after TDRE has been set to 1, then
write a 0 in TDRE
This bit is set to 1 when:
(Initial value)
1. TE = 0
2. TDRE = 1 at the end of transmission of a character
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a
multiprocessor format in asynchronous communication mode. This bit retains its previous value in
synchronous mode, when a multiprocessor format is not used, or when the RE bit is cleared to 0
even if a multiprocessor format is used.
MPB can be read but not written.
Bit 1: MPB
0
1
Description
Multiprocessor bit = 0 in receive data.
Multiprocessor bit = 1 in receive data.
(Initial value)
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit inserted
in transmit data when a multiprocessor format is used in asynchronous communication mode. The
MPBT bit is double-buffered in the same way as TSR and TDR. The MPBT bit has no effect in
synchronous mode, or when a multiprocessor format is not used.
Bit 0: MPBT
0
Description
Multiprocessor bit = 0 in transmit data.
Multiprocessor bit = 1 in transmit data.
(Initial value)
245