HD64F3437TF16 Datasheet, PDF (89/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by a reset, but is not initialized in the software standby mode.
Bit 0: RAME
0
1
Description
The on-chip RAM is disabled.
The on-chip RAM is enabled.
(Initial value)
3.3 Mode Control Register (MDCR)
Bit
7
6
5
4
3
2
1
0
EXPE^*1
—
—
—
—
—
MDS1 MDS0
Initial value
—^{* 2}
1
1
0
0
1
—^{* 2}
—^{* 2}
Read/Write R/W^*2
—
—
—
—
—
R
R
Notes: *1 H8/3437SF (S-mask model, single-power-supply on-chip flash memory version) only.
Otherwise, this is a reserved bit that is always read as 1.
*2 Determined by the mode pins (MD₁ and MD₀).
The mode control register (MDCR) is an 8-bit register that indicates the operating mode of the
chip.
Bit 7—Expanded Mode Enable (EXPE): Functions only in the H8/3437SF (S-mask model,
single-power-supply on-chip flash memory version). For details, see section 21.1.6, Mode Control
Register (MDCR).
In models other than the H8/3437SF, this is a reserved bit that cannot be modified and is always
read as 1.
Bits 6 and 5—Reserved: These bits cannot be modified and are always read as 1.
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bit 2—Reserved: This bit cannot be modified and is always read as 1.
Bits 1 and 0—Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the
mode pins (MD₁ and MD₀), thereby indicating the current operating mode of the chip. MDS1
corresponds to MD₁ and MDS0 to MD₀. These bits can be read but not written. When the mode
control register is read, the levels at the mode pins (MD₁ and MD₀) are latched in these bits.
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