HD64F3437TF16 Datasheet, PDF (297/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

In receiving, the SCI operates as follows.
1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit.
2. Receive data is shifted into RSR in order from LSB to MSB.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI makes the following checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in SMR.
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit
is checked.
c. Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR.
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one of
the checks fails (receive error), the SCI operates as indicated in table 12.10.
Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1.
Be sure to clear the error flags.
4. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the
SCI requests an RXI (receive-end) interrupt. If one of the error flags (ORER, PER, or FER) is
set to 1 and the RIE bit in SCR is also set to 1, the SCI requests an ERI (receive-error)
interrupt.
Table 12.10 Receive Error Conditions and SCI Operation
Receive Error
Overrun error
Framing error
Abbreviation
ORER
FER
Condition
Receiving of next data ends
while RDRF is still set to 1
in SSR
Stop bit is 0
Parity error
PER
Parity of receive data differs
from even/odd parity setting
in SMR
Data Transfer
Receive data not loaded from
RSR into RDR
Receive data loaded from
RSR into RDR
Receive data loaded from
RSR into RDR
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