HD64F3437TF16 Datasheet, PDF (193/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

8.2.5 Timer Control/Status Register (TCSR)
Bit
Initial value
Read/Write
7
ICFA
0
R/(W)*
6
ICFB
0
R/(W)*
5
ICFC
0
R/(W)*
4
ICFD
0
R/(W)*
3
OCFA
0
R/(W)*
2
OCFB
0
R/(W)*
1
OVF
0
R/(W)*
0
CCLRA
0
R/W
Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits.
TCSR is an 8-bit readable and partially writable register that contains the seven interrupt flags and
specifies whether to clear the counter on compare-match A (when the FRC and OCRA values
match).
TCSR is initialized to H'00 by a reset and in the standby modes.
Timing is described in section 8.4, Operation.
Bit 7—Input Capture Flag A (ICFA): This status bit is set to 1 to flag an input capture A event.
If BUFEA = 0, ICFA indicates that the FRC value has been copied to ICRA. If BUFEA = 1, ICFA
indicates that the old ICRA value has been moved into ICRC and the new FRC value has been
copied to ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7: ICFA
0
1
Description
To clear ICFA, the CPU must read ICFA after it has been set to 1, then write a
0 in this bit.
(Initial value)
This bit is set to 1 when an FTIA input signal causes the FRC value to be
copied to ICRA.
Bit 6—Input Capture Flag B (ICFB): This status bit is set to 1 to flag an input capture B event.
If BUFEB = 0, ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = 1, ICFB
indicates that the old ICRB value has been moved into ICRD and the new FRC value has been
copied to ICRB.
ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6: ICFB
0
1
Description
To clear ICFB, the CPU must read ICFB after it has been set to 1, then write a
0 in this bit.
(Initial value)
This bit is set to 1 when an FTIB input signal causes the FRC value to be
copied to ICRB.
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