HD64F3437TF16 Datasheet, PDF (187/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

8.1.4 Register Configuration
Table 8.2 lists the registers of the free-running timer module.
Table 8.2 Register Configuration
Name
Abbreviation R/W
Initial
Value
Address
Timer interrupt enable register
TIER
R/W
H'01
H'FF90
Timer control/status register
TCSR
R/(W)^*1
H'00
H'FF91
Free-running counter (high)
FRC (H)
R/W
H'00
H'FF92
Free-running counter (low)
FRC (L)
R/W
H'00
H'FF93
Output compare register A/B (high)^*2
OCRA/B (H)
R/W
H'FF
H'FF94^*2
Output compare register A/B (low)^*2
OCRA/B (L)
R/W
H'FF
H'FF95^*2
Timer control register
TCR
R/W
H'00
H'FF96
Timer output compare control register TOCR
R/W
H'E0
H'FF97
Input capture register A (high)
ICRA (H)
R
H'00
H'FF98
Input capture register A (low)
ICRA (L)
R
H'00
H'FF99
Input capture register B (high)
ICRB (H)
R
H'00
H'FF9A
Input capture register B (low)
ICRB (L)
R
H'00
H'FF9B
Input capture register C (high)
ICRC (H)
R
H'00
H'FF9C
Input capture register C (low)
ICRC (L)
R
H'00
H'FF9D
Input capture register D (high)
ICRD (H)
R
H'00
H'FF9E
Input capture register D (low)
ICRD (L)
R
H'00
H'FF9F
Notes: *1 Software can write a 0 to clear bits 7 to 1, but cannot write a 1 in these bits.
*2 OCRA and OCRB share the same addresses. Access is controlled by the OCRS
bit in TOCR.
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