HD64F3437TF16 Datasheet, PDF (351/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bit 2—Input Buffer Full Interrupt Enable 2 (IBFIE2): Enables or disables the IBF2 interrupt
to the slave CPU.
Bit 2: IBFIE2
0
1
Description
IDR2 input buffer full interrupt is disabled
IDR2 input buffer full interrupt is enabled
(Initial value)
Bit 1— Input Buffer Full Interrupt Enable 1 (IBFIE1): Enables or disables the IBF1 interrupt
to the slave CPU.
Bit 1: IBFIE1
0
1
Description
IDR1 input buffer full interrupt is disabled
IDR1 input buffer full interrupt is enabled
(Initial value)
Bit 0—Fast Gate A₂₀ Enable (FGA20E): Enables or disables the fast A₂₀ gate function. When the
fast A₂₀ gate is disabled, a regular-speed A₂₀ gate signal can be implemented by using software to
manipulate the P8₁ output.
Bit 0: FGA20E
0
1
Description
Disables fast A₂₀ gate function
Enables fast A₂₀ gate function
(Initial value)
14.2.3 Input Data Register 1 (IDR1)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
4
IDR4
—
R
W
3
IDR3
—
R
W
2
IDR2
—
R
W
1
IDR1
—
R
W
0
IDR0
—
R
W
IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the
host processor. When CS₁ is low, information on the host data bus is written into IDR1 at the
rising edge of IOW. The HA₀ state is also latched into the C/D bit in STR1 to indicate whether the
written information is a command or data.
The initial values of IDR1 after a reset or standby are undetermined.
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