HD64F3437TF16 Datasheet, PDF (461/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

(7) Design a current margin into the programming voltage (V_PP) power supply. Ensure that
V_PP will not depart from 12.0 ±0.6 V (11.4 V to 12.6 V) during programming or erasing.
Programming and erasing may become impossible outside this range.
(8) Ensure that peak overshoot does not exceed the rated value at the FV_PP and MD₁ pins.
Connect decoupling capacitors as close to the FV_PP and MD₁ pins as possible.
Also connect decoupling capacitors to the MD₁ pin in the same way when boot mode is used.
12 V
1.0 µF
12 V
1.0 µF
0.01 µF
FV_PP
0.01 µF
MD₁
H8/3434F
Note: Also connect decoupling capacitors to the MD₁ pin in the same way when boot mode is used.
Figure 19.21 V_PP Power Supply Circuit Design (Example)
(9) Use the recommended algorithms for programming and erasing flash memory. These
algorithms are designed to program and erase without subjecting the device to voltage stress and
without sacrificing the reliability of programmed data.
Before setting the program (P) or erase (E) bit in the flash memory control register (FLMCR), set
the watchdog timer to ensure that the P or E bit does not remain set for more than the specified
time.
(10) For details on interrupt handling while flash memory is being programmed or erased, see the
notes on NMI interrupt handling in section 19.4.9, Interrupt Handling during Flash Memory
Programming and Erasing.
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