HD64F3437TF16 Datasheet, PDF (253/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

11.2.2 Timer Control/Status Register (TCSR)
Bit
Initial value
Read/Write
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
3
2
1
— RST/NMI CKS2 CKS1
1
0
0
0
—
R/W
R/W
R/W
Note: * Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit.
0
CKS0
0
R/W
TCSR is an 8-bit readable/writable register that selects the timer mode and clock source and
performs other functions. (TCSR is write-protected by a password. See section 11.2.3, Register
Access, for details.)
Bits 7 to 5 and bit 3 are initialized to 0 by a reset and in the standby modes. Bits 2 to 0 are
initialized to 0 by a reset, but retain their values in the standby modes.
Bit 7—Overflow Flag (OVF): Indicates that the watchdog timer count has overflowed.
Bit 7: OVF
0
1
Description
To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0
in this bit
(Initial value)
Set to 1 when TCNT changes from H'FF to H'00
Bit 6—Timer Mode Select (WT/IT): Selects whether to operate in watchdog timer mode or
interval timer mode. When TCNT overflows, an WOVF interrupt request is sent to the CPU in
interval timer mode. For watchdog timer mode, a reset or NMI interrupt is requested.
Bit 6: WT/IT
0
1
Description
Interval timer mode (WOVF request)
Watchdog timer mode (reset or NMI request)
(Initial value)
Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5: TME
0
1
Description
TCNT is initialized to H'00 and stopped
(Initial value)
TCNT runs and requests a reset or an interrupt when it overflows
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