HD64F3437TF16 Datasheet, PDF (438/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

BRER:
MOV.W
CMP.W
BNE
BRA
#H'0BB8, R4
R4,
R6
ERASE1
ABEND2
;
; Erase-verify executed 3000 times?
; If erase-verify not executed 3000 times, erase again
; If erase-verify executed 3000 times, branch to ABEND2
;———< Block address table used in erase-verify> ———
.ALIGN 2
ERVADR: .DATA.W H'0000
; SB0
.DATA.W H'0080
; SB1
.DATA.W H'0100
; SB2
.DATA.W H'0180
; SB3
.DATA.W H'0200
; SB4
.DATA.W H'0400
; SB5
.DATA.W H'0800
; SB6
.DATA.W H'0C00
; SB7
.DATA.W H'1000
; LB0
.DATA.W H'2000
; LB1
.DATA.W H'4000
; LB2
.DATA.W H'6000
; LB3
.DATA.W H'8000
; FLASH END
EOWARI: Erase end
ABEND2: Erase error
Loop Counter Values in Programs and Watchdog Timer Overflow Interval Settings: The
setting of #a, #b, #c, #d, and #e values in the programs depends on the clock frequency. Tables
19.9 (1) and (2) indicate sample loop counter settings for typical clock frequencies. However, #e is
set according to table 19.10.
As a software loop is used, calculated values including percent errors may not be the same as
actual values. Therefore, the values are set so that the total programming time and total erase time
do not exceed 1 ms and 30 s, respectively.
The maximum number of writes in the program, N, is set to 50.
Programming and erasing in accordance with the flowcharts is achieved by setting #a, #b, #c, and
#d in the programs as shown in tables 19.9 (1) and (2). #e should be set as shown in table 19.10.
Wait state insertion is inhibited in these programs. If wait states are to be used, the setting should
be made after the program ends. The setting value for the watchdog timer (WDT) overflow time is
calculated based on the number of instructions between starting and stopping of the WDT,
including the write time and erase time. Therefore, no other instructions should be added between
starting and stopping of the WDT in this program example.
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