HD64F3437TF16 Datasheet, PDF (407/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

19.1.5 Input/Output Pins
Flash memory is controlled by the pins listed in table 19.3.
Table 19.3 Flash Memory Pins
Pin Name
Programming power
Mode 1
Mode 0
Transmit data
Receive data
Abbreviation
FV _PP
MD₁
MD₀
TxD₁
RxD₁
Input/Output
Power supply
Input
Input
Output
Input
Function
Apply 12.0 V
H8/3434F operating mode setting
H8/3434F operating mode setting
SCI1 transmit data output
SCI1 receive data input
The transmit data and receive data pins are used in boot mode.
19.1.6 Register Configuration
The flash memory is controlled by the registers listed in table 19.4.
Table 19.4 Flash Memory Registers
Name
Abbreviation
R/W
Initial Value Address
Flash memory control register FLMCR
R/W^*2
H'00^*2
H'FF80
Erase block register 1
EBR1
R/W^*2
H'F0^*2
H'FF82
Erase block register 2
EBR2
R/W^*2
H'00^*2
H'FF83
Wait-state control register^*1
WSCR
R/W
H'08
H'FFC2
Notes: *1 The wait-state control register controls the insertion of wait states by the wait-state
controller, frequency division of clock signals for the on-chip supporting modules by the
clock pulse generator, and emulation of flash-memory updates by RAM in on-board
programming mode.
*2 In modes 2 and 3 (on-chip flash memory enabled), the initial value is H'00 for FLMCR
and EBR2, and H'F0 for EBR1. In mode 1 (on-chip flash memory disabled), these
registers cannot be modified and always read H'FF.
Registers FLMCR, EBR1, and EBR2 are only valid when writing to or erasing flash memory, and
can only be accessed while 12 V is being applied to the FV_PP pin.
When 12 V is not applied to the FV_PP pin, in mode 2 addresses H'FF80 to H'FF83 are external
address space, and in mode 3 these addresses cannot be modified and always read H'FF.
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