HD64F3437TF16 Datasheet, PDF (617/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Table 23.22 Timing Conditions of On-Chip Supporting Modules
Conditions: V_CC = 3.0 V to 5.5 V, V_CCB = 3.0 V to 5.5 V, V_SS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C (regular specifications), Ta = –40 to
+85˚C (wide-range specifications)
Item
FRT
TMR
PWM
SCI
Ports
HIF read
cycle
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock pulse width
Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock pulse width
(single edge)
Timer clock pulse width
(both edges)
Timer output delay time
Input clock cycle (Async)
(Sync)
Transmit data delay time (Sync)
Receive data setup time (Sync)
Receive data hold time (Sync)
Input clock pulse width
Output data delay time
Input data setup time
Input data hold time
CS/HA₀ setup time
CS/HA₀ hold time
IOR pulse width
HDB delay time
HDB hold time
HIRQ delay time
Symbol
t_FTOD
t_FTIS
t_FTCS
t_FTCWH
t_FTCWL
t_TMOD
t_TMRS
t_TMCS
t_TMCWH
t_TMCWL
t_PWOD
t_Scyc
t_TXD
t_RXS
t_RXH
t_SCKW
t_PWD
t_PRS
t_PRH
t_HAR
t_HRA
t_HRPW
t_HRD
t_HRF
t_HIRQ
Condition
10MHz
Min
Max
—
150
80
—
80
—
1.5
—
—
150
80
—
80
—
1.5
—
2.5
—
—
150
4
—
6
—
—
200
150
—
150
—
0.4
0.6
—
150
80
—
80
—
10
—
10
—
220
—
—
200
0
40
—
200
Unit
ns
ns
ns
t_cyc
Test Conditions
Fig. 23.13
Fig. 23.14
ns
Fig. 23.15
ns
Fig. 23.17
ns
Fig. 23.16
t_cyc
t_cyc
ns
Fig. 23.18
t_cyc
Fig. 23.19
t_cyc
ns
ns
ns
t_Scyc Fig. 23.20
ns
Fig. 23.21
ns
ns
ns
Fig. 23.22
ns
ns
ns
ns
ns
588