HD64F3437TF16 Datasheet, PDF (354/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

14.2.7 Output Data Register 2 (ODR2)
Bit
7
ODR7
Initial value
—
Slave Read/Write R/W
Host Read/Write R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
3
ODR3
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
0
ODR0
—
R/W
R
ODR2 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the
host processor. The ODR2 contents are output on the host data bus when HA₀ is low, CS₂ is low,
and IOR is low.
The initial values of ODR2 after a reset or standby are undetermined.
14.2.8 Status Register 2 (STR2)
Bit
7
6
5
4
3
2
1
0
DBU DBU DBU DBU
C/D
DBU
IBF
OBF
Initial value
0
0
0
0
0
0
0
0
Slave Read/Write R/W
R/W
R/W
R/W
R
R/W
R
R
Host Read/Write R
R
R
R
R
R
R
R
STR2 is an 8-bit register that indicates status information during host interface processing. Bits 3,
1, and 0 are read-only bits to both the host and slave processors.
STR2 is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D): Receives the HA₀ input when the host processor writes to IDR2,
and indicates whether IDR2 contains data or a command.
Bit 3: C/D
0
1
Description
Contents of IDR2 are data
Contents of IDR2 are a command
(Initial value)
325