HD64F3437TF16 Datasheet, PDF (601/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Condition C Condition B Condition A
10 MHz
12 MHz
16 MHz
Item
Symbol Min Max Min Max Min Max Unit
Ports Output data delay t_PWD
time
— 150 — 100 — 100 ns
Input data setup
t_PRS
time
80 —
50 —
50 — ns
HIF
read
cycle
HIF
write
cycle
Input data hold time t_PRH
CS/HA₀ setup time t_HAR
CS/HA₀ hold time t_HRA
IOR pulse width
t_HRPW
HDB delay time
t_HRD
HDB hold time
t_HRF
HIRQ delay time
t_HIRQ
CS/HA₀ setup time t_HAW
CS/HA₀ hold time t_HWA
IOW pulse width
t_HWPW
HDB High-speed t_HDW
setup GATE A₂₀
time not used
80 —
10 —
10 —
220 —
— 200
0
40
— 200
10 —
10 —
100 —
50 —
50 —
10 —
10 —
120 —
— 100
0
25
— 120
10 —
10 —
60 —
30 —
50 — ns
10 — ns
10 — ns
120 — ns
— 100 ns
0
25 ns
— 120 ns
10 — ns
10 — ns
60 — ns
30 — ns
High-speed
GATE A₂₀
used
85 —
55 —
45 —
HDB hold time
t_HWD
25 —
15 —
15 — ns
GA₂₀ delay time
t_HGA
— 180 — 90
— 90 ns
Note: * In the F-ZTAT LH version, V_CC = 3.0 V to 5.5 V, V_CCB = 3.0 V to 5.5 V.
Test
Conditions
Fig. 23.21
Fig. 23.22
Fig. 23.23
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