HD64F3437TF16 Datasheet, PDF (602/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Table 23.11 I²C Bus Timing
Conditions: V_CC = 2.7 V to 5.5 V*, V_CCB = 2.7 V to 5.5 V*, V_SS = 0 V, Ta = –20°C to +75°C,
ø ≥ 5 MHz
Item
Symbol Min
Typ Max Unit Test Conditions Note
SCL clock
t _SCL
cycle time
12 t_cyc
—
—
ns
Fig. 23.24
SCL clock
t _SCLH
high pulse
width
3 t_cyc
—
—
ns
SCL clock
t _SCLL
low pulse
width
5 t_cyc
—
—
ns
SCL and SDA t_Sr
—
rise time
—
1000 ns Normal mode
100 kbits/s (max)
20 + 0.1C_b —
300
High-speed mode
400 kbits/s (max)
SCL and SDA t_Sf
—
fall time
—
300 ns Normal mode
100 kbits/s (max)
20 + 0.1C_b —
300
High-speed mode
400 kbits/s (max)
SDA bus-free t_BUF
time
5 t_cyc
—
—
ns
SCL start
t _STAH
condition
hold time
3 t_cyc
—
—
ns
SCL resend t_STAS
start condition
setup time
3 t_cyc
—
—
ns
SDA stop
condition
t _STOS
setup time
3 t_cyc
—
—
ns
SDA data
setup time
t _SDAS
0.5 t_cyc
—
—
ns
SDA data
t _SDAH
0
hold time
—
—
ns
SDA load
C_b
—
capacitance
—
400 pF
Note: * In the F-ZTAT LH version, V_CC = 3.0 V to 5.5 V, V_CCB = 3.0 V to 5.5 V.
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