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HD64F3437TF16 Datasheet, PDF (612/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.
Item
Symbol Min
Typ Max
Test
Unit Conditions
Analog supply voltage*1
AVCC
3.0
— 5.5
V During
operation
2.0
— 5.5
While idle or
when not in
use
RAM standby voltage
VRAM
2.0
——
V
Notes: *1 Even when the A/D and D/A converters are not used, connect AVCC to power supply VCC
and keep the applied voltage between 2.0 V and 5.5 V. At this time, make sure AVref ≤
AVCC.
*2 Current dissipation values assume that VIH min = VCC – 0.5 V, VCCB – 0.5 V, VIL max =
0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off.
*3 For these values it is assumed that VRAM ≤ VCC < 3.0 V and VIH min = VCC × 0.9, VCCB × 0.9,
VIL max = 0.3 V.
*4 P67 to P60 include supporting module inputs multiplexed with them.
*5 IRQ2 includes ADTRG multiplexed with it.
*6 Applies when IICS = IICE = 0. The output low level is determined separately when the
bus drive function is selected.
*7 The characteristics of PA7 to PA4, KEYIN15 to KEYIN12, P97/WAIT, SDA, and
P86/IRQ5/SCK1, SCL depend on VCCB; the characteristics of all other pins depend on
VCC.
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