HD64F3437TF16 Datasheet, PDF (665/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

SSR—Serial Status Register
H'8C
SCI1
Bit
Initial value
Read/Write
7
TDRE
1
R/(W) *
6
5
RDRF ORER
0
0
R/(W) * R/(W)*
4
FER
0
R/(W) *
3
PER
0
R/(W) *
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Multiprocessor Bit Transfer
0 Multiprocessor bit = 0 in transmit data.
1 Multiprocessor bit = 1 in transmit data.
Multiprocessor Bit
0 Multiprocessor bit = 0 in receive data.
1 Multiprocessor bit = 1 in receive data.
Transmit End
0 Cleared by reading TDRE = 1, then writing 0 in TDRE.
1 Set to 1 when TE = 0, or when TDRE = 1 at the end of
character transmission.
Parity Error
0 Cleared by reading PER = 1, then writing 0 in PER.
1 Set when a parity error occurs (parity of receive data
does not match parity selected by O/E bit in SMR).
Framing Error
0 Cleared by reading FER = 1, then writing 0 in FER.
1 Set when a framing error occurs (stop bit is 0).
Overrun Error
0 Cleared by reading ORER = 1, then writing 0 in ORER.
1 Set when an overrun error occurs (next data is completely
received while RDRF bit is set to 1).
Receive Data Register Full
0 Cleared by reading RDRF = 1, then writing 0 in RDRF.
1 Set when one character is received normally and transferred from RSR to RDR.
Transmit Data Register Empty
0 Cleared by reading TDRE = 1, then writing 0 in TDRE.
1 Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = 0.
Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits.
636