HD64F3437TF16 Datasheet, PDF (305/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Receiving Serial Data: Follow the procedure in figure 12.15 for receiving serial data. When
switching from asynchronous mode to synchronous mode, be sure to check that PER and FER are
cleared to 0. If PER or FER is set to 1 the RDRF bit will not be set and both transmitting and
receiving will be disabled.
1
Initialize
1. SCI initialization: the receive data function of the
RxD pin is selected automatically.
Start receiving
2. Receive error handling: if a receive error occurs,
read the ORER bit in SSR then, after executing
the necessary error handling, clear ORER to 0.
Read ORER bit in SSR
Neither transmitting nor receiving can resume
while ORER remains set to 1. When clock
output mode is selected, receiving can be halted
ORER = 1?
Yes 2
temporarily by receiving one dummy byte and
causing an overrun error. When preparations
to receive the next data are completed, clear
No
3
Read RDRF in SSR
Error handling
the ORER bit to 0. This causes receiving to
resume, so return to the step marked 2 in the
flowchart.
No
RDRF = 1?
Yes
Read receive data
4
from RDR, and clear
RDRF bit to 0 in SSR
Finished
No
receiving?
Yes
3. SCI status check and receive data read: read
the serial status register (SSR), check that
RDRF is set to 1, then read receive data from
the receive data register (RDR) and clear RDRF
to 0. Transition of the RDRF bit from 0 to 1
can be reported by an RXI interrupt.
4. To continue receiving serial data: read RDR and
clear RDRF to 0 before the MSB (bit 7) of the
current frame is received.
Clear RE to 0 in SCR
End
Start error handling
Overrun error handling
Clear ORER to 0 in SSR
Return
Figure 12.15 Sample Flowchart for Serial Receiving
276