HD64F3437TF16 Datasheet, PDF (70/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Before Execution of BCLR Instruction
Input/output
Pin state
DDR
DR
P4₇
Input
Low
0
1
P4₆
Input
High
0
0
P4₅
Output
Low
1
0
P4₄
Output
Low
1
0
P4₃
Output
Low
1
0
P4₂
Output
Low
1
0
P4₁
Output
Low
1
0
P4₀
Output
Low
1
0
Execution of BCLR Instruction
BCLR #0, @P4DDR ; clear bit 0 in data direction register
After Execution of BCLR Instruction
Input/output
Pin state
DDR
DR
P4₇
Output
Low
1
1
P4₆
Output
High
1
0
P4₅
Output
Low
1
0
P4₄
Output
Low
1
0
P4₃
Output
Low
1
0
P4₂
Output
Low
1
0
P4₁
Output
Low
1
0
P4₀
Input
High
0
0
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P4₀DDR is cleared to 0, making P4₀ an input pin. In addition, P4₇DDR and P4₆DDR
are set to 1, making P4₇ and P4₆ output pins.
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