HD64F3437TF16 Datasheet, PDF (433/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Flowchart for Erasing Multiple Blocks
Start
Set erase block registers
(set bits of blocks to be erased to 1)
Write 0 data to all addresses to be
erased (prewrite)^*1
n=1
Enable watchdog timer^*2
Select erase mode (E bit = 1 in FLMCR)
Wait (X) ms^*5
Clear E bit
Disable watchdog timer
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (t_VS1) µs^*5
Erasing
ends
Notes: *1 Program all addresses to be
erased by following the prewrite
flowchart.
*2 Set the watchdog timer
overflow interval to the value
indicated in table 19.10.
*3 For the erase-verify dummy
write, write H'FF with a byte
transfer instruction.
*4 Read the data to be verified
with a byte transfer instruction.
When erasing two or more
blocks, clear the bits of erased
blocks in the erase block
register, so that only unerased
blocks will be erased again.
*5 X: 10 ms
t_VS1: 4 µs or more
t_VS2: 2 µs or more
N: 3000
Set top address of block as
verify address
Erase-verify
next block
Dummy write to verify address^*3
(flash memory latches address)
Wait (t_VS2) µs^*5
No
Address + 1 → address
Verify^*4
(read data H'FF?)
OK
Last address
in block?
Yes
No go
Clear EBR bit of erased block
Erase-verify next block
All erased blocks
No
verified?
Yes
No
All erased blocks
verified?
Yes
Clear EV bit
All blocks erased?
No
(EBR1 = EBR2 = 0?)
Yes
End of erase
n ≥ N?^*5
Yes
Erase error
No
n+1→n
Figure 19.11 Multiple-Block Erase Flowchart
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