HD64F3437TF16 Datasheet, PDF(542/752 Page) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

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HD64F3437TF16 Datasheet, PDF (542/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

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Bit 4âFlash Memory Control Register Enable (FLSHE): When the FLSHE bit is set to 1, the

flash memory control registers can be read and written to. When FLSHE is cleared to 0, the flash

memory control registers are unselected. In this case, the contents of the flash memory contents

are retained.

Bit 4: FLSHE

0

1

Description

Flash memory control registers are in unselected state

Flash memory control registers are in selected state

(Initial value)

Bits 3 and 2âWait Mode Select 1 and 0 (WMS1, WMS0)

Bits 1 and 0âWait Count 1 and 0 (WC1, WC0)

These bits control insertion of wait states by the wait-state controller. For details, see section 5,

Wait-State Controller.

21.3 On-Board Programming Modes

When an on-board programming mode is selected, the on-chip flash memory can be programmed,

erased, and verified. There are two on-board programming modes: boot mode and user

programming mode. Table 21.6 indicates how to select the on-board programming modes. User

programming mode operation can be performed by setting control bits with software. A state

transition diagram for flash memory related modes is shown in figure 21.2.

Table 21.6 On-Board Programming Mode Selection

Mode Selection

MD1

MD0

P92

P91

P90

Boot mode

0

0

1

1

1

User programming

1

0

â

â

â

mode

1

21.3.1 Boot Mode

To use boot mode, a user program for programming and erasing the flash memory must be

provided in advance on the host machine (which may be a personal computer). Serial

communication interface (SCI) channel 1 is used in asynchronous mode.

When a reset state is executed after the H8/3437SF pins have been set to boot mode, the built-in

boot program is activated, and the on-board update routine provided in the host is transferred

sequentially to the H8/3437SF using the serial communication interface (SCI). The H8/3437SF

writes the on-board update routine received via the SCI to the on-board update routine area in the

on-chip RAM. After the transfer is completed, execution branches to the first address of the on-

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