HD64F3437TF16 Datasheet, PDF (140/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

7.3.2 Register Configuration and Descriptions
Table 7.4 summarizes the port 2 registers.
Table 7.4 Port 2 Registers
Name
Port 2 data direction register
Port 2 data register
Port 2 input pull-up control
register
Abbreviation
P2DDR
P2DR
P2PCR
Read/Write
W
R/W
R/W
Initial Value
Address
H'FF (mode 1)
H'FFB1
H'00 (modes 2 and 3)
H'00
H'FFB3
H'00
H'FFAD
Port 2 Data Direction Register (P2DDR)
Bit
7
6
5
4
3
2
1
0
Mode 1
P2₇DDR P2₆DDR P2₅DDR P2₄DDR P2₃DDR P2₂DDR P2₁DDR P2₀DDR
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
—
Modes 2 and 3
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P2DDR controls the input/output direction of each pin in port 2.
Mode 1: The P2DDR values are fixed at 1. Port 2 consists of upper address output pins. P2DDR
values cannot be modified and are always read as 1.
In hardware standby mode, the address bus is in the high-impedance state.
Mode 2: A pin in port 2 is used for address output if the corresponding P2DDR bit is set to 1, and
for general input if this bit is cleared to 0.
Mode 3: A pin in port 2 is used for general output if the corresponding P2DDR bit is set to 1, and
for general input if this bit is cleared to 0.
In modes 2 and 3, P2DDR is a write-only register. Read data is invalid. If read, all bits always read
1. P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby
mode it retains its existing values, so if a transition to software standby mode occurs while a
P2DDR bit is set to 1, the corresponding pin remains in the output state.
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