HD64F3437TF16 Datasheet, PDF (410/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bits 7 to 4—Reserved: These bits cannot be modified, and are always read as 1.
Bits 3 to 0—Large Block 3 to 0 (LB3 to LB0): These bits select large blocks (LB3 to LB0) to be
programmed and erased.
Bits 3 to 0:
LB3 to LB0
0
1
Description
Block (LB3 to LB0) is not selected
Block (LB3 to LB0) is selected
(Initial value)
19.2.3 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that designates small flash-memory blocks for programming and erasure.
EBR2 is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to FV_PP
pin. When a bit in EBR2 is set to 1, the corresponding block is selected and can be programmed
and erased. Figure 19.2 and table 19.6 show a block map.
Bit
Initial value*
Read/Write
7
SB7
0
R/W*
6
SB6
0
R/W*
5
SB5
0
R/W*
4
SB4
0
R/W*
3
SB3
0
R/W*
2
SB2
0
R/W*
1
SB1
0
R/W*
0
SB0
0
R/W*
Note: * The initial value is H'00 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip ROM
disabled), this register cannot be modified and always reads H'FF. For information on
accessing this register, refer to in section 19.7, Flash Memory Programming and Erasing
Precautions (11).
Bits 7 to 0—Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be
programmed and erased.
Bits 7 to 0:
SB7 to SB0
0
1
Description
Block (SB7 to SB0) is not selected
Block (SB7 to SB0) is selected
(Initial value)
381