HD64F3437TF16 Datasheet, PDF (324/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bit 1—General Call Address Recognition Flag (ADZ): When the addressing format is selected
(FS = 0) in slave receive mode, this flag is set to 1 if the first byte following a start condition is the
general call address (H'00).
ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 1: ADZ
0
1
Description
General call address not recognized
(Initial value)
This bit is cleared to 0 at the following times:
• When ICDR data is written (transmit mode) or read (receive mode)
• When ADZ is read while ADZ = 1, then 0 is written in ADZ
General call address recognized
This bit is set to 1 when the general call address is detected in slave receive
mode
Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data in acknowledgement mode. In
transmit mode, after the receiving device receives data, it returns acknowledge data, and this data
is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in
this bit is sent to the transmitting device.
When this bit is read, if TRS = 1, the value loaded from the bus line is read. If TRS = 0, the value
set by internal software is read.
Bit 0: ACKB
0
1
Description
Receive mode: 0 is output at acknowledge output timing
(Initial value)
Transmit mode: indicates that the receiving device has acknowledged the data
Receive mode: 1 is output at acknowledge output timing
Transmit mode: indicates that the receiving device has not acknowledged the
data
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