HD64F3437TF16 Datasheet, PDF (46/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Pin No.
Type
FP-100B,
Symbol TFP-100B I/O Name and Function
I/O ports
P9₇ to P9₀ 16 to 19,
22 to 25
I/O Port 9: An 8-bit input/output port. The
direction of each bit (except for P9₆) can be
selected in the port 9 data direction register
(P9DDR). P9₇ is powered by I/O buffer
power supply V_CCB.
PA₇ to PA₀ 10, 11, 20, I/O Port A: An 8-bit input/output port with
21, 30, 31,
programming MOS input pull-ups. The
47, 48
direction of each bit can be selected in the
port A data direction register (PADDR). PA₇
to PA₄ are powered by I/O buffer power
supply V_CCB. Features a bus drive function.
PB₇ to PB₀ 57, 58, 68, I/O Port B: An 8-bit input/output port with
69, 80, 81,
programming MOS input pull-ups. The
90, 91
direction of each bit can be selected in the
port B data direction register (PBDDR).
Note:
In this chip, except for the S-mask model (single-power-supply specification), the same pin
is used for STBY and FV_PP. When this pin is driven low, a transition is made to hardware
standby mode. This occurs not only in the normal operating modes (modes 1, 2, and 3), but
also when programming flash memory with a PROM writer. When using a PROM
programmer to program dual-power-supply flash memory, therefore, the PROM
programmer specifications should provide for this pin to be held at the V_CC level except
when programming (FV_PP = 12 V).
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