HD64F3437TF16 Datasheet, PDF (88/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

• F-ZTAT Version
Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description
0
0
0
Settling time = 8,192 states
(Initial value)
1
Settling time = 16,384 states
1
0
Settling time = 32,768 states
1
Settling time = 65,536 states
1
0
0
Settling time = 131,072 states
1
Settling time = 1,024 states
1
—
Unused
Note:
When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted.
If a period exceeding øp/1,024 (e.g. øp/2,048) is specified when selecting the 8-bit timer,
PWM timer, or watchdog timer clock, the counter in the timer will not count up normally
when 1,024 states is specified for the settling time. To avoid this problem, set the STS value
just before the transition to software standby mode (before executing the SLEEP
instruction), and re-set the value of STS2 to STS0 to a value from 000 to 100 directly after
software standby mode is cleared by an interrupt.
Bit 3—External Reset (XRST): Indicates the source of a reset. A reset can be generated by input
of an external reset signal, or by a watchdog timer overflow when the watchdog timer is used.
XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer
overflow.
Bit 3: XRST
0
1
Description
Reset was caused by watchdog timer overflow.
Reset was caused by external input.
(Initial value)
Bit 2—NMI Edge (NMIEG): Selects the valid edge of the NMI input.
Bit 2: NMIEG
0
1
Description
An interrupt is requested on the falling edge of the NMI input.
An interrupt is requested on the rising edge of the NMI input.
(Initial value)
Bit 1—Host Interface Enable (HIE): Enables or disables the host interface function. When
enabled, the host interface processes host-slave data transfers, operating in slave mode.
Bit 1: HIE
0
1
Description
The host interface is disabled.
The host interface is enabled (slave mode).
(Initial value)
59